LTC2259CUJ-16-TRPBF データシートの表示（PDF） - Linear Technology
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LTC2259CUJ-16-TRPBF Datasheet PDF : 28 Pages
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LTC2259-16
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
tL
ENC Low Time (Note 8)
(Note 10)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
1
80
MHz
l 5.93
6.25
500
ns
l 2.00
6.25
500
ns
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l 5.93
6.25
500
ns
l 2.00
6.25
500
ns
tAP
Sample-and-Hold Acquisition Delay
Time
0
ns
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
tD
tC
tSKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
CL = 5pF (Note 8)
CL = 5pF (Note 8)
tD – tC (Note 8)
Full Data Rate Mode
Double-Data Rate Mode
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
5.0
Cycles
5.5
Cycles
Digital Data Outputs (LVDS Mode)
tD
tC
tSKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
CL = 5pF (Note 8)
CL = 5pF (Note 8)
tD – tC (Note 8)
l
1.1
1.8
3.2
ns
l
1
1.5
2.7
ns
l
0
0.3
0.6
ns
Pipeline Latency
5.5
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
CS to SCK Setup Time
tH
SCK to CS Setup Time
tDS
SDI Setup Time
tDH
SDI Hold Time
tDO
SCK Falling to SDO Valid
Write Mode
l
40
Readback Mode, CSDO = 20pF, RPULLUP = 2k l
250
l
5
l
5
l
5
l
5
Readback Mode, CSDO = 20pF, RPULLUP = 2k l
ns
ns
ns
ns
ns
ns
125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 80MHz, LVDS outputs with internal
termination disabled, differential ENC+/ENC– = 2VP-P sine wave, input
range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 80MHz, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted.
Note 10: Recommended operating conditions.
225916f
6
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