LPC8N04 データシートの表示（PDF） - NXP Semiconductors.
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LPC8N04
NXP Semiconductors.
LPC8N04 Datasheet PDF : 39 Pages
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NXP Semiconductors
LPC8N04
32-bit ARM Cortex-M0+ microcontroller
LPC8N04
Product data sheet
Table 4. Pad description of the HVQFN24 package
Pad Symbol Type Description
Supply
7
VDDBAT supply positive supply voltage
8
VSS
supply ground
GPIO[1]
1
PIO0_0 I/O GPIO
WAKEUP I
deep power-down mode wake-up pin[2]
2
PIO0_1 I/O GPIO
CLKOUT O
clock output
3
PIO0_2 I/O GPIO
SSEL
I
SPI/SSP serial select line
14
PIO0_3 I/O GPIO
CT16B_M0 O
16-bit timer match output 0
11
PIO0_4 I/O GPIO
SCL
I/O I2C-bus SCL clock line
12
PIO0_5 I/O GPIO
SDA
I/O I2C-bus SDA data line
4
PIO0_6 I/O GPIO
SCLK
I/O SPI/SSP serial clock line
13
PIO0_7 I/O GPIO
CT16B_M1 O
16-bit timer match output 1
5
PIO0_8 I/O GPIO
MISO
O
SPI/SSP master-in slave-out line
6
PIO0_9 I/O GPIO
MOSI
I
SPI/SSP master-out slave-in line
15
PIO0_10 I/O GPIO
CT32B_M0 O
32-bit timer match output 0
SWCLK I
ARM SWD clock
16
PIO0_11 I/O GPIO
CT32B_M1 O
32-bit timer match output 1
SWDIO I/O ARM SWD I/O
Radio
20
LA
A
NFC antenna/coil terminal A
19
LB
A
NFC antenna/coil terminal B
Reset
9
RESETN I
external reset input[3]
[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation
of port 0 pads depends on the function selected through the IOCONFIG register block.
[2] If external wake-up is enabled on this pad, it must be pulled HIGH before entering deep power-down mode
and pulled LOW for a minimum of 100 s to exit deep power-down mode.
[3] A LOW on this pad resets the device. This reset causes I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. It has weak pull-up to VDDBAT.
All information provided in this document is subject to legal disclaimers.
Rev. 1.3 — 15 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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