M48T212VSH データシートの表示（PDF） - STMicroelectronics
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M48T212VSH Datasheet PDF : 35 Pages
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Operation
M48T212V
Table 2. Operating modes
Mode
VCC
E
G
W
Deselect
VIH
X
X
WRITE
READ
3.0V to 3.6V
VIL
X
VIL
VIL
VIL
VIH
READ
VIL
VIH
VIH
Deselect
VSO to VPFD (min)(1)
X
X
X
Deselect
≤ VSO(1)
X
X
X
1. See Table 14 on page 28 for details.
Note:
X = VIH or VIL; VSO = Battery back-up switchover voltage
Table 3. Truth table for SRAM bank select
Mode
VCC
Select
3.0V to 3.6V
Deselect
Deselect
Deselect
VSO to VPFD (min)(1)(
≤ VSO(1)
1. See Table 14 on page 28 for details.
EX
Low
Low
High
X
X
A
Low
High
X
X
X
E1CON
Low
High
High
High
High
Note:
X = VIH or VIL; VSO = Battery back-up switchover voltage
Figure 4. Chip enable control and bank select timing
DQ7-DQ0
High-Z
DIN
DOUT
High-Z
High-Z
High-Z
E2CON
High
Low
High
High
High
Power
Standby
Active
Active
Active
CMOS standby
Battery back-up
Power
Active
Active
Standby
CMOS standby
Battery back-up
EX
A
E1CON
E2CON
tEXPD
tEXPD
tAPD
AI02639
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