ISL6208CHRZ-T データシートの表示（PDF） - Renesas Electronics
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ISL6208CHRZ-T Datasheet PDF : 12 Pages
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ISL6208C
1000
QU =100nC
900 QL = 200nC
800
QU = 50nC
QL = 100nC
QU = 50nC
QL = 50nC
700
600
QU = 20nC
500
QL =50nC
400
300
200
100
0 0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 11. POWER DISSIPATION vs FREQUENCY
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices (both
upper and lower FETs) could cause increased PHASE ringing,
which may lead to voltages that exceed the absolute maximum
rating of the devices. When PHASE rings below ground, the
negative voltage could add charge to the bootstrap capacitor
through the internal bootstrap diode. Under worst-case
conditions, the added charge could overstress the BOOT and/or
PHASE pins. To prevent this from happening, the user should
perform a careful layout inspection to reduce trace inductances,
and select low lead inductance MOSFETs and drivers. D2PAK and
DPAK packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must be
used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase and
gate nodes significantly:
• Avoid using vias for decoupling components where possible,
especially in the BOOT-to-PHASE path. Little or no use of vias
for VCC and GND is also recommended. Decoupling loops
should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC) should be
short and wide, and avoid using vias. If vias must be used, two
or more vias per layer transition is recommended.
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN of the
upper FET and the SOURCE of the lower FET as thermally
possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal pad of
the DFN to the power ground with multiple vias is recommended.
This heat spreading allows the part to achieve its full thermal
potential.
FN8395 Rev 1.00
Jun 1, 2016
Page 10 of 12
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