UDA1351TS データシートの表示（PDF） - Philips Electronics

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UDA1351TS

96 kHz IEC 958 audio DAC

Philips Electronics 

Philips Semiconductors

96 kHz IEC 958 audio DAC

Preliminary specification

UDA1351TS

8 FUNCTIONAL DESCRIPTION

The UDA1351TS is a low cost audio IEC 958 decoder with

an on-board DAC. The minimum audio input sampling

frequency conforming to the IEC958 standard is 28.0 kHz

and the maximum audio sampling frequency is 100.0 kHz.

8.1 Clock regeneration and lock detection

The UDA1351TS contains an on-board PLL for

regenerating a system clock from the IEC 958 input

bitstream.

Note: If there is no input signal, the PLL generates a

minimum frequency and the output spectrum shifts

accordingly. Since the analog output does not have an

analog mute, this means noise that is out of band under

normal conditions can move into the audio band.

When the on-board clock locks to the incoming frequency,

the lock indicator bit is set and can be read via the

L3 interface. Internally, the PLL lock indication is

combined with the PCM status bit of the input data stream.

When both the IEC 958 decoder and the on-board clock

have locked to the incoming signal and the input data

stream is PCM data, pin LOCK will be asserted. However,

when the IC is locked but the PCM status bit reports

non-PCM data, pin LOCK is returned to LOW level.

The lock indication output can be used, for example, for

muting purposes. The lock signal can be used to drive an

external analog muting circuit to prevent out of band noise

from becoming audible when the PLL runs at its minimum

frequency (e.g. when there is no SPDIF input signal).

8.2 Mute

The UDA1351TS is equipped with a cosine roll-off mute in

the DSP data path of the DAC part. Muting the DAC, by

pin MUTE (in static mode) or via bit MT (in L3 mode), will

result in a soft mute, as shown in Fig.3. The cosine roll-off

soft mute takes 32 x 32 samples = 24 ms at 44.1 kHz

sampling frequency.

When operating in the L3 control mode, the device will

mute on start-up. In L3 mode, it is necessary to explicitly

switch off the mute for audio output by means of the MT bit

in the L3 register.

In the L3 mode, pin MUTE does not have any function (the

same holds for several other pins) and can either be left

open circuit (since it has an internal pull-down resistor) or

be connected to ground.

handbook, h1alfpage

mute

factor

0.8

MGU119

0.6

0.4

0.2

0

0

5

10

15

20

25

t (ms)

Fig.3 Mute as a function of raised cosine roll-off.

8.3 Auto mute

By default, the DAC outputs will be muted until the IC is

locked, regardless of the level on pin MUTE (in static

mode) or the state of bit MT of the sound feature register

(in L3 mode). In this way, only valid data will be passed to

the outputs. This mute is done in the SPDIF interface and

is a hard mute, not a cosine roll-off mute.

If needed, this muting can be bypassed by setting

bit AutoMT to logic 0 via the L3 interface. As a result, the

IC will no longer mute during out-of-lock situations.

8.4 Data path

The UDA1351TS data path consists of the IEC 958

decoder, the audio feature processor, digital interpolator

and noise shaper and the DACs.

8.4.1 IEC 958 INPUT

The UDA1351TS IEC 958 decoder features an on-chip

amplifier with hysteresis, which amplifies the IEC 958 input

signal to CMOS level (see Fig.4).

All 24 bits of data for left and right are extracted from the

input bitstream as well as several of the IEC 958 key

channel-status bits.

2000 Mar 28

8

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