DS2482-800 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2482-800 Datasheet PDF : 22 Pages
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DS2482-800: Eight-Channel 1-Wire Master
PARAMETER
Write 0 Low Time
SYMBOL
tW0L
Write 0 Recovery Time
tREC0
Reset Low Time
tRSTL
Presence-Detect Sample Time
Sampling for Short and
Interrupt
Reset High Time
Presence Pulse Mask Start
Presence Pulse Mask Stop
I²C-Pins (Note 8) See Figure 10
tMSP
tSI
tRSTH
tppm1
tppm2
CONDITIONS
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
(Note 7)
(Note 7)
LOW Level Input Voltage
VCC = 2.9V to 3.7V
VIL
VCC = 4.5V to 5.5V
HIGH Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
3mA Sink Current
Output Fall Time from VIhmin to
VILmax with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current Each I/O Pin with
an Input Voltage Between
0.1VCCmax and 0.9VCCmax
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warm-Up Time
VIH
Vhys
VOL
tof
tSP
Ii
Ci
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Cb
tOSCWUP
SDA and SCL pins only
(Notes 9, 10)
(Note 9)
(Notes 11, 12)
(Note 13)
(Note 14)
(Note 15)
MIN TYP
60
64
7.1
7.5
5.0
5.3
2.8
3.0
570
600
68.4
72
66.5
70
7.1
7.5
7.6
8
0.7
0.75
554.8 584
70.3
74
9.5
10
57
60
MAX
68
7.9
5.6
3.2
630
75.6
73.5
7.9
8.4
0.8
613.2
77.7
10.5
63
UNITS
µs
µs
µs
µs
µs
µs
µs
µs
-0.5
0.7 ×
VCC
0.05 ×
VCC
0.25 ×
VCC
0.22 ×
V
VCC
VCC +
0.5V
V
V
0.4
V
60
250
ns
50
ns
-10
10
µA
10
pF
0
400
kHz
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0.9
µs
250
ns
0.6
µs
1.3
µs
400
pF
100
µs
3 of 22
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