Q67120-C850 データシートの表示（PDF） - Siemens AG

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Q67120-C850

16-Bit CMOS Single-Chip Microcontrollers with/without oscillator prescaler with 32 KByte Flash EPROM

Siemens AG 

SAB 88C166(W)

Flash Erase Example

This example describes the Flash erase algorithm. The four banks of the Flash memory can be

erased separately. The algorithm erases the Flash memory bank, which is selected by bitfield BE in

the FCR. Start address and size of the selected Flash bank have to be considered.

Note: Before a bank can be erased, all its contents must be programmed to ‘0000H’. This is

required by the physics of the Flash memory cells and is done with the Flash programming

algorithm already described.

Figure 8

Memory Banking for Flash Erasure

The FCR has been defined with an EQU assembler directive. Accesses to bits of the FCR are made

via an auxiliary GPR, as the FCR itself is not bit-addressable.

The shown example uses the following assumptions:

q Pin VPP/EBC1 receives a proper VPP supply voltage.

q The SAB 88C166(W) runs at 20 MHz CPU clock (absolute time delays refer to it).

q The Flash memory is mapped to segment 1. All DPPs are set correctly.

Semiconductor Group

23

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