CXP508L4 データシートの表示（PDF） - Sony Semiconductor
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CXP508L4 Datasheet PDF : 11 Pages
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CXP508L4/508L6
Electrical Characteristics
DC characteristics
(Ta = –20 to +75°C, VSS = 0V)
Item
Symbol
Pin
High level output
voltage
VOH
Low level output
voltage
VOL
PA to PF∗1,
PX0 to PX2,
PY0, PY1,
VL (VOL only)
Condition
VDD = 2.4V, IOH = –0.3mA∗2
VDD = 2.4V, IOH = –0.5mA∗2
VDD = 2.4V, IOH = –5µA∗3
VDD = 2.4V, IOH = –10µA∗3
VDD = 2.4V, IOL = 1.0mA
VDD = 2.4V, IOL = 2.0mA
Min. Typ. Max. Unit
1.8
V
1.4
V
1.8
V
1.4
V
0.4 V
0.6 V
IIH
IILE
Input current
IILR
IIL
High impedance
I/O leakage current
IIZ
EXTAL∗4
RST∗5
PA to PF∗6,
PX0 to PX2∗6,
PX3∗8, PY0∗7,
PY1∗7, PY2∗8,
PY3∗8, INT1∗8,
WP∗8, RST∗5
VDD = 3.5V, VIH = 3.5V
VDD = 3.5V, VIL = 0.4V
VDD = 3.5V
VI = 0, 3.5V
0.3
–0.3
–1.5
20 µA
–20 µA
–200 µA
–1.0 mA
±5 µA
Common output
impedance
Segment output
impedance
RCOM
RSEG
COM0 to COM3
SEG0 to SEG15
SEG16 to SEG23∗1
VDD = 3.5V
VLC1 = 2.65V
VLC2 = 1.75V
VLC3 = 0.88V
3
5 kΩ
5
15 kΩ
Current power
supply
IDD
IDDSP
VDD
VDD = 3.5V During external clock
1MHz operation
Entire output pins open
SLEEP mode
1.3 4 mA
0.6 1.2 mA
IDDS
STOP mode
7 µA
Input capacitance CIN
VLC1 to VLC3,
COM0 to COM3,
SEG0 to SEG15,
SEG16 to SEG23∗1,
Other pins than VDD,
VSS
Clock 1MHz
0V other than the measured
pins
10 20 pF
∗1 The PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when
the combined pins are selected as the segment output.
∗2 It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and
PY1 are when the inverter output circuit is selected.
∗3 It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance.
∗4 It is when the crystal or ceramic oscillation circuit is selected.
∗5 The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage
current when non-resistance is selected.
∗6 The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is
selected, and specify the leakage current when in the port state during the 3-state output circuit or standby
is selected at high impedance.
∗7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and
specify the leakage current when in the port state during standby is selected at high impedance.
∗8 The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current.
–5–
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