MTL001 データシートの表示（PDF） - Myson Century Inc

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コンポーネント説明

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MTL001

XGA Flat Panel Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTL001

(Rev. 0.95)

3.5 Host Interface

General Description

The primary function of Host Interface is to provide the interface between MTL001 and external CPU by 2-

wire I2C Bus or Direct Bus selected by the input pin BUSSEL. It can generate all the I/O decoded control

timing to control all the registers in MTL001. The other function is Screen Write, which allows users to clear

frame buffer, and display output as well.

3.5.1 I2C Serial Bus

The I2C serial interface uses 2 wires, SCK (clock) and SDA(data I/O) respectively. The SCK is used as the

sampling clock and SDA is a bi-directional signal for the data. The communication must be started with a

valid START condition, concluded with STOP condition and acknowledged by ACK condition by the receiver.

The I2C bus device address of MTL001 is 0111010x.

AD[0] SCK, serial bus clock.

AD[1] SDA, bi-directional serial bus data.

The START condition means a HIGH to LOW transition of SDA when SCK is high, the STOP condition

means a LOW to HIGH transition of SDA when SCK is high. And data of SDA can only change when SCK is

low. Ref. Fig.3.5.1.

SDA

SCK

START

DATA

CHANGE

DATA

CHANGE

STOP

Fig. 3.5.1 START, STOP ,and DATA definition

The I2C interface supports Random Write, Sequential Write, Current Address Read, Random Read and

Sequential Read operations.

¨ Random Write

For Random Write operation, it contains the slave address with R/W bit set to 0 and the word address which

is comprised of 8 bits that provides the access to any one of the 256 bytes in the selected memory range.

Upon receipt of the word address, MTL003 responds with an Acknowledge and waits for the next eight bits of

data again, responding with an Acknowledge, and then the master generates a stop condition. Ref. Fig.3.5.2.

Revision 0.95

- 17 -

2000/06/14

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