HEF4104BT(2016) データシートの表示（PDF） - NXP Semiconductors.
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HEF4104BT Datasheet PDF : 14 Pages
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Nexperia
HEF4104B
Quad low-to-high voltage translator with 3-state outputs
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Fig 4.
The shaded area shows the permissible operating range.
VDD(B) as a function of VDD(A)
10. Dynamic characteristics
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Table 7. Dynamic characteristics
Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
Extrapolation formula[1] Min Typ Max Unit
tPHL
HIGH to LOW
An to Bn, Bn; see Figure 5
propagation delay
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
tPLH
LOW to HIGH
An to Bn, Bn; see Figure 5
propagation delay
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
tTHL
HIGH to LOW output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
tTLH
LOW to HIGH output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
tPHZ
HIGH to OFF-state OE to Bn, Bn; see Figure 6
propagation delay
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
143 ns + (0.55 ns/pF)CL - 170 340 ns
69 ns + (0.23 ns/pF)CL
- 80 160 ns
57 ns + (0.16 ns/pF)CL
- 65 135 ns
143 ns + (0.55 ns/pF)CL - 170 340 ns
69 ns + (0.23 ns/pF)CL
- 80 160 ns
62 ns + (0.16 ns/pF)CL
-
70 140 ns
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
- 60 120 ns
- 30 60 ns
- 20 40 ns
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
- 60 120 ns
- 30 60 ns
- 20 40 ns
- 70 135 ns
- 55 110 ns
- 60 120 ns
HEF4104B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 29 March 2016
© Nexperia B.V. 2017. All rights reserved
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