EPF10K200SQI599-3N データシートの表示（PDF） - Altera Corporation

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EPF10K200SQI599-3N

Embedded Programmable Logic Device

Altera Corporation 

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

Figure 4. FLEX 10KE Device in Single-Port RAM Mode

Dedicated

Clocks

Dedicated Inputs

& Global Signals

Chip-Wide

Reset

Row Interconnect

EAB Local

Interconnect (1)

2

4

8, 4, 2, 1

8, 9, 10, 11

DQ

DQ

DQ

RAM/ROM

256 × 16

Data

In

512

1,024

×

×

8

4

2,048 × 2

Data Out

4, 8, 16, 32

DQ

4, 8

Address

Write Enable

4, 8, 16, 32

Column Interconnect

Note:

(1) EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E,

EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels.

EABs can be used to implement synchronous RAM, which is easier to use

than asynchronous RAM. A circuit using asynchronous RAM must

generate the RAM write enable signal, while ensuring that its data and

address signals meet setup and hold time specifications relative to the

write enable signal. In contrast, the EAB’s synchronous RAM generates its

own write enable signal and is self-timed with respect to the input or write

clock. A circuit using the EAB’s self-timed RAM must only meet the setup

and hold time specifications of the global clock.

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