M34D64-W データシートの表示（PDF） - STMicroelectronics

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M34D64-W

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

M34D64-W

Figure 9. Read mode sequences

Current

Address

Read

ACK

NO ACK

Dev sel

Data out

R/W

Device operation

Random

Address

Read

ACK

ACK

ACK

ACK

NO ACK

Dev sel *

Byte addr

Byte addr

Dev sel *

Data out

R/W

R/W

Sequential

Current

Read

ACK

ACK

Dev sel

Data out 1

R/W

ACK

NO ACK

Data out N

Sequential

Random

Read

ACK

ACK

ACK

ACK

ACK

Dev sel *

Byte addr

Byte addr

Dev sel *

Data out 1

R/W

R/W

3.10

ACK

NO ACK

Data out N

AI01105d

1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)

must be identical.

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

3.11

Random Address Read

A dummy Write is performed to load the address into the address counter (as shown in

Figure 9.: Read mode sequences) but without sending a Stop condition. Then, the bus

master sends another Start condition, and repeats the Device Select Code, with the

Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the

addressed byte. The bus master must not acknowledge the byte, and terminates the transfer

with a Stop condition.

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