CS51312GDR16 データシートの表示（PDF） - ON Semiconductor
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CS51312GDR16 Datasheet PDF : 22 Pages
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CS51312
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC1 < 14 V; 9.0 V ≤ VCC2 ≤ 20 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Good Output
PWRGD Sink Current
PWRGD Upper Threshold
VFB = 1.7 V, VPWRGD = 1.0 V
% of Nominal DAC Code
0.5
4.0
15
mA
5.0
8.5
12
%
PWRGD Lower Threshold
% of Nominal DAC Code
−12
−8.5
−5.0
%
PWRGD Output Low Voltage
Overvoltage Protection (OVP) Output
VFB = 1.7 V, IPWRGD = 500 μA
−
0.2
0.3
V
OVP Source Current
OVP = 1.0 V
1.0
10
25
mA
OVP Threshold
% of Nominal DAC Code
5.0
8.5
12
%
OVP Pull−Up Voltage
General Electrical Specifications
IOVP = 1.0 mA, VCC1 − VOVP
−
1.1
1.5
V
VCC1 Monitor Start Threshold
VCC1 Monitor Stop Threshold
Hysteresis
−
−
Start−Stop
7.9
8.4
8.9
V
7.6
8.1
8.6
V
0.15
0.3
0.6
V
VCC1 Supply Current
VCC2 Supply Current
No Load on GATE(H), GATE(L)
No Load on GATE(H), GATE(L)
−
9.5
16
mA
−
2.5
4.5
mA
PACKAGE PIN #
SO−16
1, 2, 3, 4, 5
6
7
8
9
10
11
12
13
14
15
16
PACKAGE PIN DESCRIPTION
PIN SYMBOL
VID0−VID4
VFB
VOUT
VCC1
VCC2
GATE(H)
GND
GATE(L)
OVP
PWRGD
COFF
COMP
FUNCTION
Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left
open. VID4 selects the DAC range. When VID4 is high (logic one), the Error
Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When
VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V
with 50 mV increments.
Error amp inverting input, PWM comparator non−inverting input, current limit
comparator non−inverting input, PWRGD and OVP comparator input.
Current limit comparator inverting input.
Input power supply pin for the internal circuitry and low side gate driver. Decou-
ple with filter capacitor to GND.
Input power supply pin for the high side gate driver. Decouple with filter capaci-
tor to GND.
High side switch FET driver pin.
Ground pin and IC substrate connection.
Low side synchronous FET driver pin.
Overvoltage protection pin. Drives high when overvoltage condition is detected
on VFB.
Power Good Output. Open collector output drives low when VFB is out of regu-
lation.
Off−Time Capacitor pin. A capacitor from this pin to GND sets the off time for
the regulator.
Error amp output. PWM comparator inverting input. A capacitor on this pin pro-
vides error amp compensation, and determines the Soft Start and hiccup tim-
ing. Pulling COMP below 1.1 V (typ) turns off both GATE drivers and shuts
down the regulator.
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