MGA-43040 データシートの表示（PDF） - Avago Technologies
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MGA-43040 Datasheet PDF : 16 Pages
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Application Schematic
Vdd1
Vdd2
Vdd3
Idq1
Idq2
Idq3
C3
C4
Z=50 Ω
E=8.3 deg
F=2.35 GHz
C7
Z=50 Ω
E=7.0 deg
F=2.35 GHz
C10
C8
Z=50 Ω
C13
E=8.3 deg
F=2.35 GHz
1
RFin
C1
Z=50 Ω
F=2.35 GHz
Top View
C2 RFout
Z=50 Ω
F=2.35 GHz
C18 C20 C22
C24
I_Vddbias
C25
C26
Vc1 Vc2 Vc3 Vddbias Vdet
Figure 6. Application circuit in demonstration board
Notes
1. All capacitors on supply lines are bypass capacitors.
2. C1/C2 are RF coupling capacitors.
3. Idq1= 60 mA, Idq2 = 110 mA, Idq3 = 180.0 mA, I_Vddbias = 16.0 mA at Vdd1,2,3=VddBias=5.0 V. Idq1/2/3 are adjusted by voltages to CMOS-
compatible control pins Vc1/2/3, respectively. These typical bias currents were obtained with Vc1/2/3 voltages in Figure 2. Adjustment of these
currents enable optimum bias conditions to be achieved for best linearity and efficiency for a given modulation type.
3
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