ISL97671IRZ-T データシートの表示（PDF） - Renesas Electronics
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ISL97671IRZ-T
Renesas Electronics
ISL97671IRZ-T Datasheet PDF : 27 Pages
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ISL97671
25%. Hitting of the upper threshold will also set the thermal fault
bit of the Fault/Status register 0x02. Unless disabled via the EN
pin, the device stays in an active state throughout, allows the
external processor to interrogate the fault condition.
For the extensive fault protection conditions, please refer to
Figure 25 and Table 1 for details.
VIN
LX
FAULT
DRIVER
IMAX ILIMIT LOGIC
O/P
SHORT
FET
DRIVER
LX
OVP
VSC
VOUT
CH0
VSET/2
REG
FAULT/
STATUS
REGISTER
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET +
Q0 VSET +
-
-
PWM/OC0/SC0
SMBUS/I2C
CONTROL
LOGIC
DC CURRENT
PWM/OC5/SC5
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
CH5
Q5
TABLE 1. PROTECTIONS TABLE
CASE FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
VOUT REGULATED
BY
1 CH0 Short Circuit
Upper Over-Temperature CH0 ON and burns power.
Protection limit (OTP) not
triggered and CH0 < 4V
CH1 through CH5 Normal
Highest VF of
CH1 through CH5
2 CH0 Short Circuit
3 CH0 Short Circuit
Upper OTP triggered but
VCH0 < 4V
Upper OTP not triggered
but CH0 > 4V
All channels go off until chip cooled
and then comes back on with
current reduced to 76%. Subsequent
OTP triggers will reduce IOUT further.
Same as CH0
CH1 disabled after 6 PWM cycle
time-out.
CH1 through CH5 Normal
Highest VF of
CH1 through CH5
Highest VF of
CH1 through CH5
4 CH0 Open Circuit
with infinite
resistance
Upper OTP not triggered
and CH0 < 4V
VOUT will ramp to OVP. CH1 will time- CH1 through CH5 Normal
out after 6 PWM cycles and switch
off. VOUT will drop to normal level.
Highest VF of
CH1 through CH5
5 CH0 LED Open Circuit Upper OTP not triggered CH1 remains ON and has highest VF, CH1 through CH5 ON, Q1 through VF of CH0
but has paralleled
Zener
and CH0 < 4V
thus VOUT increases.
Q5 burn power
FN7631 Rev.4.00
Sep 7, 2017
Page 15 of 27
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