ISL97671IRZ-T データシートの表示（PDF） - Renesas Electronics

部品番号

コンポーネント説明

メーカー

ISL97671IRZ-T

6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control

Renesas Electronics 

ISL97671

TABLE 1. PROTECTIONS TABLE (Continued)

CASE FAILURE MODE

DETECTION MODE

FAILED CHANNEL ACTION

GOOD CHANNELS ACTION

VOUT REGULATED

BY

6 CH0 LED Open Circuit Upper OTP triggered but All channels go off until chip cooled Same as CH0

but has paralleled CH0 < 4V

and then comes back on with

Zener

current reduced to 76%. Subsequent

OTP triggers will reduce IOUT further

VF of CH0

7 CH0 LED Open Circuit Upper OTP not triggered CH0 remains ON and has highest VF, VOUT increases, then CH-X

VF of CH0

but has paralleled but CHx > 4V

thus VOUT increases.

switches OFF after 6 PWM cycles.

Zener

This is an unwanted shut off and

can be prevented by setting OVP

at an appropriate level.

8 Channel-to-Channel Lower OTP triggered but Any channel at below the target current will fault out after 6 PWM cycles. Highest VF of

VF too high

CHx < 4V

Remaining channels driven with normal current.

CH0 through CH5

9 Channel-to-Channel

VF too high

10 Output LED stack

voltage too high

Upper OTP triggered but

CHx < 4V

VOUT > VOVP

All channels go off until chip cooled and then comes back on with current Highest VF of

reduced to 76%. Subsequent OTP triggers will reduce IOUT further

CH0 through CH5

Any channel that is below the target current will time-out after 6 PWM Highest VF of

cycles, and VOUT will return to the normal regulation voltage required for CH0 through CH5

other channels.

11 VOUT/LX shorted to

GND at start-up or

VOUT shorted in

operation

LX current and timing are

monitored.

OVP pins monitored for

excursions below 20% of

OVP threshold.

The chip is permanently shutdown 31ms after power-up if VOUT/Lx is

shorted to GND.

SMBCLK

VIH

VIL

SMBDAT

VIH

VIL

P tBUF S

tLOW

tHD:STA

tR

tF

tHD:DAT

tHIGH

tSU:DAT

tSU:STA

S

NOTES:

SMBus/I2C Description

S = start condition

P = stop condition

A = acknowledge

A = not acknowledge

R/W = read enable at high; write enable at low

FIGURE 26. SMBUS/I2C INTERFACE

tSU:STO

P

FN7631 Rev.4.00

Sep 7, 2017

Page 16 of 27

Share Link: