CY7C1049BNV33-20VXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C1049BNV33-20VXC Datasheet PDF : 8 Pages
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AC Test Loads and Waveforms
3.3V
R1 317Ω
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
THÉVENIN EQUIVALENT
OUTPUT
167Ω
R2
351Ω
(b)
1.73V 3.3V
GND
RiseTime:1 V/ns
CY7C1049BNV33
ALL INPUT PULSES
90%
10%
90%
10%
Fall time:
1 V/ns
AC Switching Characteristics[4] Over the Operating Range
-12
-15
-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tpower
VCC (typical) to the First Access[5]
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
Write Cycle[8, 9]
1
1
1
µs
12
15
20
ns
12
15
20
ns
3
3
3
ns
12
15
20
ns
6
7
8
ns
0
0
0
ns
6
7
8
ns
3
3
3
ns
6
7
8
ns
0
0
0
ns
12
15
20
ns
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
10
12
13
ns
tAW
Address Set-Up to Write End
10
12
13
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
13
ns
tSD
Data Set-Up to Write End
7
8
9
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
0
0
0
ns
3
3
3
ns
6
7
8
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.power time has to be provided initially before a read/write operation is
started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. No input may exceed VCC + 0.5V
11. .tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
Document #: 001-06432 Rev. **
Page 3 of 8
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