DSP56800FM データシートの表示（PDF） - Motorola => Freescale

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DSP56800FM

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

3.9 Serial Peripheral Interface (SPI) Timing

Table 15. SPI Timing1

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol Min Max Unit See Figure

Cycle time

Master

Slave

tC

Figures 22,

50

—

ns

23, 24, 25

25

—

ns

Enable lead time

Master

Slave

tELD

Figure 25

—

—

ns

25

—

ns

Enable lag time

Master

Slave

tELG

Figure 25

—

—

ns

100

—

ns

Clock (SCLK) high time

Master

Slave

tCH

ns Figures 22,

24

—

ns

23, 24, 25

12

—

Clock (SCLK) low time

Master

Slave

tCL

Figures 22,

24.1 —

ns

23, 24, 25

12

—

ns

Data set-up time required for inputs

Master

Slave

tDS

Figures 22,

20

—

ns

23, 24, 25

0

—

ns

Data hold time required for inputs

Master

Slave

tDH

Figures 22,

0

—

ns

23, 24, 25

2

—

ns

Access time (time to data active from high-impedance state)

tA

Slave

Figure 25

4.8

15

ns

Disable time (hold time to high-impedance state)

Slave

tD

Figure 25

3.7 15.2 ns

Data Valid for outputs

Master

Slave (after enable edge)

tDV

Figures 22,

—

4.5

ns

23, 24, 25

— 20.4 ns

Data invalid

Master

Slave

tDI

Figures 22,

0

—

ns

23, 24, 25

0

—

ns

Rise time

Master

Slave

tR

Figures 22,

— 11.5 ns

23, 24, 25

— 10.0 ns

Fall time

Master

Slave

tF

Figures 22,

—

9.7

ns

23, 24, 25

—

9.0

ns

1.Parameters listed are guaranteed by design.

32

56F826 Technical Data

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