DSP56800FM データシートの表示（PDF） - Motorola => Freescale

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DSP56800FM

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

Synchronous Serial Interface (SSI) Timing

Table 17. SSI Slave Mode1 Switching Characteristics (Continued)

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Parameter

Symbol Min Typ Max Units

Delay from SRCK high to SRFS (bl) high - Slave5

Delay from SRCK high to SRFS (wl) high - Slave5

Delay from STCK high to STFS (bl) low - Slave5

Delay from STCK high to STFS (wl) low - Slave5

Delay from SRCK high to SRFS (bl) low - Slave5

Delay from SRCK high to SRFS (wl) low - Slave5

tRFSBHS

0.1

—

46

ns

tRFSWHS

0.1

—

46

ns

tTFSBLS

-1

—

—

ns

tTFSWLS

-1

—

—

ns

tRFSBLS

-46

—

—

ns

tRFSWLS

-46

—

—

ns

STCK high to STXD enable from high impedance - Slave

STCK high to STXD valid - Slave

STFS high to STXD enable from high impedance (first bit) -

Slave

tTXES

—

—

ns

tTXVS

1

—

25

ns

tFTXES

5.5 —

25

ns

STFS high to STXD valid (first bit) - Slave

tFTXVS

6

—

27

ns

STCK high to STXD not valid - Slave

tTXNVS

11

—

13

ns

STCK high to STXD high impedance - Slave

tTXHIS

11

— 28.5

ns

SRXD Setup time before SRCK low - Slave

tSS

4

—

—

ns

SRXD Hold time after SRCK low - Slave

tHS

4

—

—

ns

Synchronous Operation (in addition to standard external clock parameters)

SRXD Setup time before STCK low - Slave

tTSS

4

—

—

SRXD Hold time after STCK low - Slave

tTHS

4

—

—

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0

in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the

frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS in the tables and in the figures.

4. 50% duty cycle

5. bl = bit length; wl = word length

56F826 Technical Data

37

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