BUK101-50DL データシートの表示（PDF） - Philips Electronics
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BUK101-50DL Datasheet PDF : 10 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK101-50DL
ID / A
30
BUK101-50DL
IS / A
100
BUK101-50DL
20
typ.
50
10
0
50
60
70
VIS / V
Fig.12. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.13. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IISL & IIS / uA
600
BUK101-50DL
500
PROTECTION LATCHED
400
IISL
300
RESET
IIS
200
100
NORMAL
0
0
2
4
6
VIS / V
Fig.14. Typical DC input characteristics, Tj = 25 ˚C.
IISL & IIS = f(VIS); protection latched & normal operation
0
0
Fig.15.
1
2
VSD / V
Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.16. Test circuit for resistive load switching times.
VIS / V & VDS / V
15
VDS
10
VIS
5
BUK101-50DL
0
0
200
400
600
time / us
Fig.17. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
April 1993
7
Rev 1.100
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