Description
Figure 6. Block diagram
STM6600 - STM6601
VCC LO
VCC VCC
(1)
RPB
(2)
RSR
+
–
VTH+
VCC
VTH–
PB
SR
GND
Glitch immunity
Edge detector debounce
Glitch immunity
Edge detector debounce
EN (EN)
Smart
logic
tREC
generator
RST
PSHOLD
RPSHOL(D3)
INT
SRD logic
1.5 V
VREF
PBOUT
CSRD
AM00237v3
1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications).
2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed
device options).
3. Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18).
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Doc ID 15453 Rev 7