ADSP-BF539 データシートの表示（PDF） - Analog Devices

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ADSP-BF539

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

Programmable Flags Cycle Timing

Table 31 and Figure 29 describe programmable flag operations.

Table 31. Programmable Flags Cycle Timing

Parameter

Timing Requirement

tWFI

Flag input pulsewidth

Switching Characteristic

tDFO

Flag output delay from CLKOUT low

ADSP-BF539/ADSP-BF539F

Minimum Maximum Unit

tSCLK + 1

ns

6

ns

CLKOUT

PFx (OUTPUT)

PFx (INPUT)

tDFO

FLAG OUTPUT

tWFI

FLAG INPUT

Figure 29. Programmable Flags Cycle Timing

Rev. PrF | Page 51 of 68 | September 2006

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