BU1425AK 데이터 시트보기 (PDF) - ROHM Semiconductor

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BU1425AK

NTSC / PAL digital RGB encoder

ROHM Semiconductor 

Multimedia ICs

4) Odd / even recognition timing in Slave mode

1. Timing based on recognition of odd conditions

The BU1425AK / AKV distinguishes whether the condi-

tions of each field (each time that VSY is input) are odd

or otherwise, and internal operation is carried out based

on that recognition after the data is input. As a result,

BU1425AK / BU1425AKV

HSY and VSY are input under input conditions appropri-

ate to the specified mode, enabling regulated output for

the first time. Odd input conditions are indicated below.

Timing that does not match these conditions is recog-

nized as an even field.

HSY

VSY

HSY

VSY

Tvl

Expanded view

Thvdiff

Fig. 18 Odd recognition conditions

Table 17: Odd recognition conditions

Parameter

VSY input L interval

Symbol

Tvl

Unit

BCLK

VSY Delay from HSY Thvdiff BCLK

∗ BCLK = One cycle of internal clock

Min.

128

HSY falling edge

– 1clk

Typ.

—

—

Max.

—

HSY Rising edge

– 2clk

24

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