AD9832BRUZ-REEL 데이터 시트보기 (PDF) - Analog Devices
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AD9832BRUZ-REEL Datasheet PDF : 28 Pages
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Data Sheet
AD9832
TIMING CHARACTERISTICS
VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A1
Limit at TMIN to TMAX (B Version)
40
16
16
50
20
20
15
20
SCLK − 5
15
5
8
8
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
1 See the Pin Configuration and Function Descriptions section.
Test Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
FSELECT, PSEL0, PSEL1 setup time before MCLK rising edge
FSELECT, PSEL0, PSEL1 setup time after MCLK rising edge
Timing Diagrams
t1
MCLK
t2
t3
Figure 3. Master Clock
SCLK
FSYNC
SDATA
t5
t4
t7
t6
t8
D15
D14
t10
t9
D2
D1
D0
Figure 4. Serial Timing
D15
D14
MCLK
FSELECT
PSEL0, PSEL1
VALID DATA
t11
VALID DATA
Figure 5. Control Timing
t11A
VALID DATA
Rev. E | Page 5 of 28
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