A610 데이터 시트보기 (PDF) - Intel

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A610

PENTIUM® PROCESSOR at iCOMP® INDEX 61075 MHz

Intel 

PENTIUM® PROCESSOR (610\75)

Note that all input pins must meet their AC/DC

specifications to guarantee proper functional

behavior.

The # symbol at the end of a signal name indicates

that the active, or asserted state occurs when the

signal is at a low voltage. When a # symbol is not

present after the signal name, the signal is active,

or asserted at the high voltage level.

Symbol

Type

Table 3. Quick Pin Reference

Name and Function

A20M#

I When the address bit 20 mask pin is asserted, the Pentium processor

(610\75) emulates the address wraparound at 1 Mbyte which occurs on the

8086. When A20M# is asserted, the Pentium processor (610\75) masks

physical address bit 20 (A20) before performing a lookup to the internal caches

or driving a memory cycle on the bus. The effect of A20M# is undefined in

protected mode. A20M# must be asserted only when the processor is in real

mode.

A31-A3

I/O As outputs, the address lines of the processor along with the byte enables

define the physical area of memory or I/O accessed. The external system

drives the inquire address to the processor on A31-A5.

ADS#

O The address status indicates that a new valid bus cycle is currently being

driven by the Pentium processor (610\75) .

AHOLD

I In response to the assertion of address hold , the Pentium processor (610\75)

will stop driving the address lines (A31-A3), and AP in the next clock. The rest

of the bus will remain active so data can be returned or driven for previously

issued bus cycles.

AP

I/O Address parity is driven by the Pentium processor (610\75) with even parity

information on all Pentium processor (610\75) generated cycles in the same

clock that the address is driven. Even parity must be driven back to the

Pentium processor (610\75) during inquire cycles on this pin in the same clock

as EADS# to ensure that correct parity check status is indicated by the Pentium

processor (610\75).

APCHK#

O The address parity check status pin is asserted two clocks after EADS# is

sampled active if the Pentium processor (610\75) has detected a parity error on

the address bus during inquire cycles. APCHK# will remain active for one clock

each time a parity error is detected.

[APICEN]

PICD1

I The Advanced Programmable Interrupt Controller Enable pin enables or

disables the on-chip APIC interrupt controller. If sampled high at the falling

edge of RESET, the APIC is enabled. APICEN shares a pin with the

Programmable Interrupt Controller Data 1 signal.

BE7#-BE5#

BE4#-BE0#

O The byte enable pins are used to determine which bytes must be written to

I/O external memory, or which bytes were requested by the CPU for the current

cycle. The byte enables are driven in the same clock as the address lines

(A31-3).

The lower four byte enables (BE3#-BE0#) are used on the Pentium processor

(610\75) as APIC ID inputs and are sampled at RESET.

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