A610 데이터 시트보기 (PDF) - Intel

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A610

PENTIUM® PROCESSOR at iCOMP® INDEX 61075 MHz

Intel 

PENTIUM® PROCESSOR (610\75)

Symbol

CLK

D/C#

D63-D0

DP7-DP0

[DPEN#]

PICD0

EADS#

EWBE#

FERR#

Type

I

O

I/O

I/O

I/O

I

I

O

Table 3. Quick Pin Reference (Contd.)

Name and Function

The clock input provides the fundamental timing for the Pentium processor

(610\75). Its frequency is the operating frequency of the Pentium processor

(610\75) external bus and requires TTL levels. All external timing parameters

except TDI, TDO, TMS, TRST#, and PICD0-1 are specified with respect to the

rising edge of CLK.

The data/code output is one of the primary bus cycle definition pins. It is driven

valid in the same clock as the ADS# signal is asserted. D/C# distinguishes

between data and code or special cycles.

These are the 64 data lines for the processor. Lines D7-D0 define the least

significant byte of the data bus; lines D63-D56 define the most significant byte

of the data bus. When the CPU is driving the data lines, they are driven during

the T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the

data bus when BRDY# is returned.

These are the data parity pins for the processor. There is one for each byte of

the data bus. They are driven by the Pentium processor (610\75) with even

parity information on writes in the same clock as write data. Even parity

information must be driven back to the Pentium processor (610\75) on these

pins in the same clock as the data to ensure that the correct parity check status

is indicated by the Pentium processor (610\75) . DP7 applies to D63-D56; DP0

applies to D7-D0.

Dual processing enable is an output of the Dual processor and an input of the

Primary processor. The Dual processor drives DPEN# low to the Primary

processor at RESET to indicate that the Primary processor should enable dual

processor mode. Since the dual processing feature is not supported on the

Pentium processor (610\75) TCP package, DPEN# should never be asserted

(low) at RESET. DPEN# shares a pin with PICD0.

This signal indicates that a valid external address has been driven onto the

Pentium processor (610\75) address pins to be used for an inquire cycle.

The external write buffer empty input, when inactive (high), indicates that a

write cycle is pending in the external system. When the Pentium processor

(610\75) generates a write, and EWBE# is sampled inactive, the Pentium

processor (610\75) will hold off all subsequent writes to all E- or M-state lines in

the data cache until all write cycles have completed, as indicated by EWBE#

being active.

The floating point error pin is driven active when an unmasked floating point

error occurs. FERR# is similar to the ERROR# pin on the Intel387™ math

coprocessor. FERR# is included for compatibility with systems using DOS-type

floating point error reporting.

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