LT1641(RevD) 데이터 시트보기 (PDF) - Linear Technology
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LT1641 Datasheet PDF : 12 Pages
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LT1641
APPLICATIO S I FOR ATIO
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recom-
mended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
high current applications. To make the system immune to
noise, the resistor divider to the ON pin needs to be close
to the chip and keep traces to VCC and GND short. A 0.1µF
capacitor from the ON pin to GND also helps reject induced
noise. Figure 16 shows a layout that addresses these
issues.
Figure 13. Overvoltage Waveforms
VIN
48V
SHORT
PIN
R1
294k
1%
UV = 37V
R2
10.2k
1%
GND
RS
0.01Ω
Q1
IRF530
D1
R5
10Ω
CMPZ
5248B
R3
143k
5%
1%
C1
R6, 10nF
1k, 5%
+
8
VCC
1
ON
7
SENSE
6
GATE
LT1641
2
FB
R7
47k
5%
R4
4.22k
1%
TIMER
5
C2
0.68µF
GND
4
3
PWRGD
Q2
MMBT5551LT1
CL
220µF
ACTIVE LOW
ENABLE MODULE
VIN+ VOUT+
ON/OFF
VIN– VOUT–
VOUT
1641 F14
Figure 14. Active Low Enable Module
18
16
14
12
10
8
6
4
2
0
8
13
18
VCC (V)
23
1641 F15
Figure 15. Gate Drive vs Supply Voltage
ILOAD
R1
LT1641
SENSE
RESISTOR, RS
R2
ILOAD
1541 F16
Figure 16. Recommended Layout for R1, R2 and RS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1641fd
11
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