MC14536BFEL 데이터 시트보기 (PDF) - ON Semiconductor

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MC14536BFEL

Programmable Timer

ON Semiconductor 

RX

PULSE

GEN.

CLOCK

CX

MC14536B

+V

16

6 8−BYPASS

VDD

9A

OUT 1

4

10 B

11 C

12 D

2 RESET

OUT 2

5

1 SET

7 CLOCK INH

15 MONO−IN

14 OSC INH

3 IN1

VSS DECODE OUT

13

8

IN1

RESET

DECODE OUT

*tw

POWERUP

*tw ≈ .00247 • RX • CX0.85

tw in msec

RX in kW

CX in pF

NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET

input low enables the chip’s internal counters. After RESET goes low, the 2n/2 negative transition of the clock input causes

DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the

output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock period)

intervals where n = the number of stages selected from the truth table.

Figure 12. Time Interval Configuration Using an External Clock, Reset, and

Output Monostable to Achieve a Pulse Output

(Divide−by−4 Configured)

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