MT28F320J3RG-15 데이터 시트보기 (PDF) - Micron Technology

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MT28F320J3RG-15

Q-FLASH™ MEMORY

Micron Technology 

128Mb, 64Mb, 32Mb

Q-FLASH MEMORY

NOTE: 1. Commands other than those shown in Table 4 are reserved for future device implementations and should not be used.

2. The SCS is also referred to as the extended command set.

3. Bus operations are defined in Table 3.

4. X = Any valid address within the device

BA = Address within the block

IA = Identifier code address; see Figure 2 and Table 15

QA = Query data base address

PA = Address of memory location to be programmed

5. ID = Data read from identifier codes

QD = Data read from query data base

SRD = Data read from status register; see Table 16 for a description of the status register bits

PD = Data to be programmed at location PA; data is latched on the rising edge of WE#

CC = Configuration code

6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.

7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.

See Block Status Register section for read identifier code data.

8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 float, which places them in High-Z.

9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.

10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count

ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third and

consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command (D0h) is

expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the WRITE-to-

BUFFER operation. Please see Figure 4, WRITE-to-BUFFER Flowchart, for additional information.

11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.

12. Attempts to issue a block erase or program to a locked block while RP# = VIH will fail.

13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.

14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.

15. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.

128Mb, 64Mb, 32Mb Q-Flash Memory

MT28F640J3_7.p65 – Rev. 6, Pub. 8/02

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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