NCP1205(2002) 데이터 시트보기 (PDF) - ON Semiconductor

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NCP1205
(Rev.:2002)

Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback

ON Semiconductor 

NCP1205

1. In BCM, every time the 65 mV line is crossed, the

switch is immediately turned–on. By accounting for

the internal Demag pin capacitance (10–15 pF

typical), you can introduce a fixed delay, which,

combined to the propagation delay, allows to precisely

re–start in the drain–source valley (minimum voltage

to reduce capacitive losses).

2. When the IC enters VFM, the VCO delivers a pulse

which is internally latched. As soon as the

demagnetization pulse appears, the logic re–starts the

MOSFET.

3. As can be seen from Figure 13, the parasitic

oscillations on the drain are subject to a natural

damping, mainly imputed to ohmic losses. At a given

point, the demag activity on the auxiliary winding

becomes too low to be detected. To avoid any re–start

problem, the TY72001 features an internal 4.0 µs

timeout delay. This timeout runs after each demag

pulse. If within 4.0 µs further to a demag pulse no

activity is detected, an internal signal is combined

with the VCO to actually re–start the MOSFET

(synchronized with Ct).

Error Amplifier and Fault Detection

The NCP1205 features an internal error amplifier solely

used to detect an overcurrent problem. The application

assumes that all the error gain associated with the precise

reference level is located on the secondary side of the SMPS.

Various solutions can be purposely implemented such as the

TL431 or a dedicated circuit like the MC33341. In the

NCP1205, the internal OPAMP is used to create a virtual

ground permanently biased at 2.5 V (Figure 14), an internal

reference level. By monitoring this virtual ground further

called V(–), we have the possibility to confirm the good

behavior of the loop. If by any mean the loop is broken

(shorted optocoupler, open LED etc.) or the regulation

cannot be reached (true output short–circuit), the OPAMP

network is adjusted in order to no longer be able to ensure

the 2.5 V virtual point V(–). If V(–) passes down the 1.5 V

level (e.g. output shorted) for a time longer than 128 ms, then

the pulses are stopped for 8 x 128 ms. The IC enters a kind

of burst mode with bunch of pulses lasting 128 ms and

repeating every 8 x 128 ms. If the loop is restored within the

8 x 128 ms period, then the pulses are back again on the

output drive (synchronized with UVLOH).

Drain Level

Valley

Switching

Possible Demag

Auxiliary Level

65 mV

0V

2

4 µs

IP = 0

Restart when Demag is too low

750.0 U

754.0 U

758.0 U

762.0 U

766.0 U

Figure 14. Core Reset Detection is done through

an Auxiliary Winding Operated in Forward

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