AD807(RevB) 데이터 시트보기 (PDF) - Analog Devices

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AD807
(Rev.:RevB)

Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming

Analog Devices 

Bandwidth

This describes the frequency at which the AD807 attenuates

sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the AD807 in dB.

Damping Factor, ζ

Damping factor, ζ describes the compensation of the second

order PLL. A larger value of ζ corresponds to more damping

and less peaking in the jitter transfer function.

Acquisition Time

This is the transient time, measured in bit periods, required for

the AD807 to lock onto input data from its free-running state.

Symmetry—Recovered Clock Duty Cycle

Symmetry is calculated as (100 × on time)/period, where on

time equals the time that the clock signal is greater than the

midpoint between its “0” level and its “1” level.

Bit Error Rate vs. Signal-to-Noise Ratio

AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is

shown in TPC 6. Wideband amplitude noise is summed with

the input data signal as shown in Figure 4. Performance is

shown for input data levels of 5 mV and 10 mV.

EPITAXX ERM504

VCM

2mV p-p

SCOPE

PROBE

AD807 QUANTIZER

BINARY

OUTPUT

VCM

a. Single-Ended Input Application

AD8015

DIFFERENTIAL

OUTPUT TIA

+OUT

–OUT

VCM

1mV p-p

SCOPE

PROBE

AD807 QUANTIZER

BINARY

OUTPUT

VCM

b. Differential Input Application

Figure 3. (a–b) Single-Ended and Differential Input

Applications

AD807

DIFFERENTIAL

SIGNAL

SOURCE

POWER

COMBINER

+

⌺

+

0.47␮F

50⍀

POWER

COMBINER

+

⌺

–

0.47␮F

POWER

SPLITTER

50⍀

75⍀

1.0␮F

PIN

D.U.T.

AD807

NIN

100⍀

100MHz FILTER

5V

NOISE

SOURCE

GND

Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio

Test: Block Diagram

AVCC2

DIFFERENTIAL

INPUT

VBE 0.8V

CURRENT SOURCES

HEADROOM 0.7V

0.5mA

AVEE

400⍀

1mA

400⍀

0.5mA

a. Quantizer Differential Input Stage

1.2V +VBE

5.9k⍀

94.6k⍀

THRADJ

AVEE

b. Threshold Adjust

VCC1

IOH

150⍀

SDOUT

150⍀

IOL

VEE

c. Signal Detect Output (SDOUT)

450⍀

450⍀

VCC2

DIFFERENTIAL

INPUT

2.5mA

VEE

d. PLL Differential Output Stage—DATAOUT(N),

CLKOUT(N)

Figure 5. (a–d) Simplified Schematics

REV. B

–5–

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