VITESSE
SEMICONDUCTOR CORPORATION
SMPTE 292M Serializer, Deserializer, and
Deserializer/Reclocker
Advance Product Information
VSC6511
Serializer Mode
Features
• 20-Bit TTL Interface at 74.25MHz or 74.25/1.001MHz
• On-chip Clock Multiplier Unit
• On-Chip Scrambler and NRZI Encoder with ENABLE
• CRC Generator with ENABLE
• 2 or 4 user configurable 75Ω cable driver outputs
• Buffered REFCLK output for easy clock distribution
• 700 mW Typical Power
The VSC6511 can be configured as a 20-bit HDTV Serializer using the MODE[1:0] pins. A 74.25 MHz TTL
REFCLK is multiplied by 20 in the Clock Multiplier Unit (CMU) to generate a 1.485GHz bit rate clock. The
CMU aligns a divided-by-20 clock with REFCLK in order to latch the 20-bit TTL data bus D[19:0] into the
Input Register. When enabled by CRC being HIGH, the data is monitored for SAV/EAV and a CRC checksum
is calculated and inserted into the data stream at the appropriate point in each video line. The data is then scram-
bled and NRZI encoded, only if this stage is enabled by SCREN=HIGH. The data is then serialized and output
on the differential outputs, SDO0/SDO0 and SDO1/SDO1, which are compliant with the SMPTE 292M cable
driving specifications. The scrambler and NRZI encoder can be disabled by setting the TTL input, SCREN to
LOW. The SDO0/SDO0 output can be disabled and forced HIGH by setting the TTL input OE0 to LOW. Simi-
larly, the SDO1/SDO1 output can be disabled and forced HIGH by setting the TTL input OE1 to LOW. When
the high-speed outputs are disabled, the true and complement outputs float HIGH.
Figure 6: Serializer Mode
D[19:10]
LUMA
CHROMA
D[9:0]
CRCEN
SCREN
REFCLK
74.25 MHz
DQ
CRC Gen
Scrambler
NRZI Encoder
Clock
Multiply
/20
x20
1.485 GHz
Serializer
OE0
*
SDO0
SDO0
ISET0
OE1
SDO1
SDO1
ISET1
CABLE DRIVER
OUTPUTS
RCLK
Page 8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52311-0, Rev 2.1
6/25/01