TDAT021G2 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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TDAT021G2 Datasheet PDF : 310 Pages
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TDAT042G5 Device Advisory
for Version 1 and 1A of the Device
Advisory
May 2001
UTOPIA (UT) (continued)
UT9. Clock Requirements for MPHY Modes
When using the TDAT042G5 in MPHY mode, receive and transmit clocks must be provided for all channels (A, B,
C, and D). Also, the packet available (PA) signal for each channel must be provided on each channel’s associated
PA pin.
Workaround
It is possible to place RxCLK[D:A] into source mode by provisioning bit 6 (CLOCK_MODE_Rx) of the UTOPIA
receive provisioning registers (addresses 0x020F, 0x0213, 0x0217, 0x021B). This will eliminate the need to supply
separate receive and transmit clocks.
Corrective Action
This is informational only. No corrective action is required for this condition.
UT10. Egress Packet Mode Overflows
In the UTOPIA modes listed below, the device will report transmit packet overflow errors when no overflows have
occurred. This occurs when the egress high watermark is set for the UTOPIA modes as shown in Table 6.
Table 6. Settings at Which Overflows Reported in Error
UTOPIA Modes
8-bit, U3+
16-bit, U2+
32-bit, U3+
Egress High Watermark Thresholds
≥0x3D
≥0x3B
≥0x37
Workaround
Set the egress high watermark threshold as shown in Table 7. If there is a delay between TxPA deassertion and
TxENB deassertion, the additional cycles should also be accounted for when setting the threshold.
Table 7. Settings to Prevent Overflows Reported in Error
UTOPIA Modes
8-bit, U3+
16-bit, U2+
32-bit, U3+
Egress High Watermark Thresholds
<0x3D
<0x3B
<0x37
Corrective Action
This condition will be addressed in future versions of the device.
16
Agere Systems Inc.
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