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Z87000

SPREAD SPECTRUM CONTROLLERS

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Z87000/Z87L00

Spread Spectrum Controllers

The loop filter is controlled by the DSP core processor. The Each frame lasts 4 ms, which corresponds to (372 + 8/22)

DSP core can implement a first order loop by setting the bits; the frame counters count from 0 to 371, with the last

1 SECOND_ORDER field to zero. Typically, the count lasting a bad longer than the other ones; at the end

BSYNC_GAIN would then be set to “divide-by-1” operation of count 371, the counters wrap around to 0.

to provide a wide closed loop bandwidth and thus a quick

acquisition of the bit clock. When the bit clock is in phase The “hop” command pulse is asserted to pin SYLE during

with the input data, the loop bandwidth can be narrowed to count “0” of the frame counter (transmit frame counter on

maintain tracking of the receive clock with minimum impact the base station).

from signal noise. To reduce the loop bandwidth, the

BSYNC_GAIN can be set to “divide-by-64” the first order

gain, while the integrated tracking error (available to the

Frame Synchronizer, Timings and

RF Interface

DSP in fields INT_SYM_ERR0 and INT_SYM_ERR1) can The frame synchronizer tracks the received frames and re-

be used by the DSP software to adjust the sets the receive frame counter. The synchronization is per-

SECOND_ORDER term.

formed by recognizing certain data patterns present in the

The bit synchronizer relies on transitions in the received bit

stream to operate. The bit inversion logic guarantees

enough transitions for all transferred data.

receive bit stream: a comparison is done on the fly be-

tween the data pattern and the incoming bit stream; when

the data match, the frame counter is reset.

At the handset, the bit synchronizer must track both fre-

quency and phase of the receive signal’s data clock. At the

base, only the phase must be tracked. The frequency is in-

herently correct since the base is the source of the sys-

tem’s data clock.

Table 2. Bit Synchronizer Control Fields

Field

Register

Bank EXT

Two possible 16-bit data patterns are pre-programmed in

the Z87000. One is named UW (Unique Word) and is used

in acquisition mode for first-time synchronization to an in-

coming signal. UW can also be used to track an acquired

signal. The second pattern is named SYNC_D and is used

to track the received data frames while voice is being

transferred. The transition from tracking UW to tracking

SYNC_D is controlled by the DSP processor through the

SYNC_SEARCH_WORD field.

BYSNC_GAIN

INT_SYM_ERR1

INT_SYM_ERR0

SECOND_ORDER

SSPSTATE

BIT_SYNC

INT_SYM-ERR0

BIT_SYNC

3 EXT2

1 EXT2

0 EXT6

1 EXT2

Frame Counters

The handset only has one frame counter, which times all

receive and transmit events. The base station has distinct

transmit and receive frame counters. When used in this

document without any explicit reference to either base or

handset, the terms “receive frame counter” and “transmit

frame counter” refer to both sides. For the handset, both

terms refer to the same unique counter.

The frame counters are clocked at the bit rate, or 93.09

kHz (2.048 MHz/22). Each count lasts one bit =

1000/93.09 = 10.74 µs.

UW Synchronization

When the Z87000 matches the UW, the receive frame

counter is reset to the value of UW_LOCATION. This value

is programmable by the DSP processor. On the handset,

where the receive frame counter is used to derive all tim-

ings, UW_LOCATION actually defines the guard time be-

tween the frequency hop command and the beginning of

data reception, which starts at FRAME_COUNTER =

(UW_LOCATION - 84) as shown in the next figure.

On the base station, data reception starts when the receive

frame counter equals (UW_LOCATION - 84), but this has

less significance since the hop pulse is synchronized with

the transmit frame counter and there is no fixed relation-

ship between transmit and receive frame counters. On the

base station, the UW_LOCATION should be set to 301.

DS96WRL0501

PRELIMINARY

1-27

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