FX980L7 데이터 시트보기 (PDF) - CML Microsystems Plc

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FX980L7

TETRA Baseband Processor

CML Microsystems Plc 

TETRA Baseband Processor

FX980

Example: To program the fifth and sixth locations of the Auxiliary SRAM with $0x01AA the

commands would be:

$0x0000⇒Cmd ; set ConfigCtrl1 all bits Low

; use default conditions

$0x0118⇒Cmd

; set ConfigCtrl2 bits 7 and 6 Low

; set ConfigCtrl2 bit 4 High

; set ConfigCtrl2 bit 3 High

; required by default for these

Reserved bits

; post-increment addresses on a

read operation

; enable read/write access to the

Auxiliary SRAM

$0xF300⇒Cmd ; read SramData LSB register

; read fourth memory location

(LSB). Post-increment pointer.

CmdRd⇒$0xF3xx ; SramData LSB register data returned ; discard this byte

$0x7002⇒Cmd ; write SramData LSB register

; write $0x02 to fifth memory

location (LSB)

$0x716A⇒Cmd ; write SramData MSB register

; write $0x6A to sixth memory

location (MSB)

$0xF000⇒Cmd ; read SramData LSB register

; read fifth memory location (LSB)

CmdRd⇒$0xF002 ; SramData LSB register data returned ; check this byte is $0x02

$0xF100⇒Cmd ; read SramData MSB register

; read sixth memory location (MSB)

CmdRd⇒$0xF16A ; SramData MSB register data returned ; check this byte is $0x6A

$0x0110⇒Cmd ; set ConfigCtrl2 bit 3 Low

; disable read/write access to the

Auxiliary SRAM

1.5.6.6 Coefficient Memory

The convention for naming filter coefficients is A1 to An, where n is given by (Filter Length + 1)/2, i.e. for the

15-tap filter, n = 8. This arises from the internal architecture of the filters and the fact that they are all “odd”

and symmetrical. Write or read operations beyond this coefficient number will be reflected about the central

coefficient e.g. the tenth read operation from the 15-tap filter would access coefficient location A6.

There is no practical reason to write or read beyond location n, but the user in any case must avoid write

operations at the (Filter Length + 1) location. This location (A0) location must be zero for the filters to operate

correctly. The global reset (N-RESET pin) establishes this condition when taken Low.

1.5.7 Register Description

This section describes in detail each of the registers and access points addressed by the Command Control

Serial Word.

© 1997 Consumer Microcircuits Limited

14

D/980/3

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