FX980L7 데이터 시트보기 (PDF) - CML Microsystems Plc

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FX980L7

TETRA Baseband Processor

CML Microsystems Plc 

TETRA Baseband Processor

FX980

Key to Register Map

Each section that follows describes in detail the operation and use of each of the registers in the device. The

registers are split into their functional groups, grouping associated registers together. Each section consists of

a Title, an Address, a Function Reference Field, a Description, and a Bit Specification.

The Function Reference Field describes the overall access available to this section (RW/W/R, where R = Read

and W = Write).

The Bit Specification describes the function of each individual bit, or a range of bits within a register. There is a

separate line for each distinct field of bits. The State column indicates the action available to each group of

bits (RW/W/R).

Register Reset State

All I/O access points (both read and write) are reset to logic zero on taking N_RESET Low, except where

explicitly shown in this document. The reset state of status bits will depend on the level of the status signal

being monitored. Other registers (both read and write) are not affected by taking N_RESET Low.

© 1997 Consumer Microcircuits Limited

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D/980/3

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