FX980L7 데이터 시트보기 (PDF) - CML Microsystems Plc

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FX980L7

TETRA Baseband Processor

CML Microsystems Plc 

TETRA Baseband Processor

FX980

$0x38-$0x39

$0x3A-$0x3B

$0x3C-$0x3F

Rx Data Path Access Points

RxDataAccess

Receive path data access point (I)

RxDataAccess

Receive path data access point (Q)

Not Used

$0x40-$0x41

$0x42-$0x43

$0x44-$0x45

$0x46-$0x47

$0x48-$0x49

$0x4A-$0x4B

$0x4C-$0x4D

$0x4E-$0x4F

Tx Data Path Registers

TxPhase

Transmit I channel phase correction registers

TxIQGainMult

Transmit I channel gain attenuation registers

TxIQOffset

Transmit I channel offset correction registers

TxPhase

Transmit Q channel phase correction registers

TxIQGainMult

Transmit Q channel gain attenuation registers

TxIQOffset

Transmit Q channel offset correction registers

TxRampUpInc

Transmit ramp-up increment registers

TxRampDnDec

Transmit ramp-down decrement registers

$0x50-$0x51

$0x52-$0x53

$0x54-$0x5F

Tx Data Path Access Points

TxDataAccess

Transmit path data access point (I)

TxDataAccess

Transmit path data access point (Q)

Not Used

$0x60-$0x61

$0x62

$0x63

$0x64-$0x6D

$0x6E-$0x6F

Self Test Registers

BISTPRSG

Built-in self test pseudo-random sequence generator

BISTControl

Built-in self test control register

Not Used

BISTCRCRegisters

Built-in self test cyclic redundancy code checkers

Not Used

$0x70-$0x73

$0x74-$0x7F

SramData

SRAM Memory Access Points

Auxiliary DAC1 memory I/O access addresses

Not Used

Note: Addresses $0x80 to $0xFF cannot be used as the MSB controls the direction of data flow:

“1” = High = Read and “0” = Low = Write.

© 1997 Consumer Microcircuits Limited

17

D/980/3

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