Chart-25 High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
• ICX282
HD
HD'
CKI
CKO
ADCLK
1
MCKO
H1A/B
H2A/B
RG
XSHP
XSHD
62
270/398/478
∗ HD’ indicates the HD which is the actual CXD2498R load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.