AD7394AR 데이터 시트보기 (PDF) - Analog Devices
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AD7394AR Datasheet PDF : 12 Pages
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AD7394/AD7395–SPECIFICATIONS
AD7394 12-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS (@ VREF IN = 2.5 V, –40؇C < TA < +85؇C, unless otherwise noted)
Parameter
Symbol
Conditions
3 V ؎ 10% 5 V ؎ 10% Units
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Relative Accuracy2
Differential Nonlinearity2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Voltage Error
Full-Scale Tempco3
N
INL
INL
DNL
DNL
VZSE
VFSE
VFSE
TCVFS
12
TA = +25°C
± 1.5
TA = –40°C, +85°C
± 2.0
TA = +25°C, Monotonic
± 0.9
Monotonic
±1
Data = 000H
4.0
TA = +25°C, +85°C, Data = FFFH ± 8
TA = –40°C, Data = FFFH
± 20
–30
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
VREF
RREF
CREF
0/VDD
2.5
5
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
IOUT
IOUT
CL
Data = 800H, ∆VOUT = 5 LSB
1
Data = 800H, ∆VOUT = 5 LSB
3
No Oscillation
100
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
INTERFACE TIMING3, 5
Clock Width High
Clock Width Low
Load Pulsewidth
Data Setup
Data Hold
Clear Pulsewidth
Load Setup
Load Hold
VIL
VIH
IIL
CIL
tCH
tCL
tLDW
tDS
tDH
tCLRW
tLD1
tLD2
0.5
VDD–0.6
10
10
50
50
30
10
30
15
30
40
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
DAC Glitch
Digital Feedthrough
Feedthrough
SR
Data = 000H to FFFH to 000H
0.05
tS
To ± 0.1% of Full Scale
70
Q
Code 7FFH to 800H to 7FFH
65
Q
15
VOUT/VREF
VREF = 1.5 VDC +1 V p-p,
Data = 000H, f = 100 kHz
–63
SUPPLY CHARACTERISTICS
Power Supply Range
Shutdown Supply Current
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD_SD
IDD
PDISS
PSS
DNL < ± 1 LSB
SHDN = 0, VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
2.7/5.5
0.1/1.5
125/200
600
0.006
NOTES
1One LSB = VREF/4096 V for the 12-bit AD7394.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3These parameters are guaranteed by design and not subject to production testing.
4Typicals represent average readings measured at +25°C.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.
12
± 1.5
± 2.0
± 0.9
±1
4.0
±8
± 20
–30
0/VDD
2.5
5
1
3
100
0.8
4.0
10
10
30
30
20
10
15
15
15
20
0.05
60
65
15
–63
2.7/5.5
0.1/1.5
125/200
1000
0.006
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
ppm/°C typ
V min/max
MΩ typ4
pF typ
mA typ
mA typ
pF typ
V max
V min
µA max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
V/µs typ
µs typ
nV/s typ
nV/s typ
dB typ
V min/max
µA typ/max
µA typ/max
µW max
%/% max
–2–
REV. 0
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