AGL060V5-QNG144 데이터 시트보기 (PDF) - Microsemi Corporation
부품명
상세내역
제조사
AGL060V5-QNG144 Datasheet PDF : 250 Pages
| |||
Datasheet Information
Revision
Changes
Page
Revision 20
(continued)
Figure 2-4 • Input Buffer Timing Model and Delays (example) has been modified for the 2-21
DIN waveform; the Rise and Fall time label has been changed to tDIN (SAR 37104).
Added missing characteristics for 3.3 V LVCMOS, 3.3 V LVCMOS Wide range, 1.2 V 2-35 to
LVCMOS, and 1.2 V LVCMOS Wide range to the following tables:
2-40,
• Table 2-38, Table 2-39, Table 2-40, Table 2-42, Table 2-43, and Table 2-44 (SARs 2-47 to
33854 and 36891)
2-49,
• Table 2-63, Table 2-64, and Table 2-65 (SAR 33854)
2-74,
2-76, and
• Table 2-127, Table 2-128, Table 2-129, Table 2-137, Table 2-138, and Table 2-139 2-77
(SAR 36891).
AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to
match Table 2-50 · AC Waveforms, Measuring Points, and Capacitive Loads (SAR
34878).
2-42
Added values for minimum pulse width and removed the FRMAX row from Table 2-173 2-105
through Table 2-188 in the "Global Tree Timing Characteristics" section. Use the through
software to determine the FRMAX for the device you are using (SAR 29271).
2-112
Revision 19
CS121 was added to the product tables in the "IGLOO Low Power Flash FPGAs" I
(September 2011) section for AGL125 (SAR 22737). CS81 was added for AGL250 (SAR 22737).
Notes indicating that device/package support is TBD for AGL250-QN132 and I to IV
AGL060-FG144 have been removed (SAR 33689).
M1AGL400 was removed from the "I/Os Per Package1" table. This device was II
discontinued in April 2009 (SAR 32450).
Dimensions for the QN48 package were added to Table 1 • IGLOO FPGAs Package II
Sizes Dimensions (SAR 30537).
The Y security option and Licensed DPA Logo were added to the "IGLOO Ordering III
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
32151).
The "In-System Programming (ISP) and Security" section and "Security" section were
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry
(SAR 32865).
I, 1-2
The following sentence was removed from the "Advanced Architecture" section:
1-3
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR
28756).
The "Specifying I/O States During Programming" section is new (SAR 21281).
1-8
Values for VCCPLL at 1.2 V –1.5 V DC core supply voltage were revised in Table 2-2 • 2-2
Recommended Operating Conditions 1 (SAR 22356).
The value for VPUMP operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR
25220).
The value for VCCPLL 1.5 V DC core supply voltage was changed from" 1.4 to 1.6 V" to
"1.425 to 1.575 V" (SAR 26551).
The notes in the table were renumbered in order of their appearance in the table (SAR
21869).
The temperature used in EQ 2 was revised from 110°C to 100°C for consistency with 2-6
the limits given in Table 2-2 • Recommended Operating Conditions 1. The resulting
maximum power allowed is thus 1.28 W. Formerly it was 1.71 W (SAR 26259).
5-2
Revision 23
Share Link: 