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ADC1002S020HL Datasheet PDF : 18 Pages
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Integrated Device Technology
ADC1002S020
Single 10 bits ADC, up to 20 MHz
Table 6. Characteristics …continued
VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted
together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vref(dif)
differential reference
voltage
VRT VRB
1.9
2.1
3.0
V
Iref
Rlad
TCRlad
reference current
ladder resistance
ladder resistor
temperature coefficient
-
7.2
-
mA
-
290
-
-
539
-
m/K
-
1860
-
ppm
Voffset
offset voltage
BOTTOM
TOP
[2] -
135
-
mV
[2] -
135
-
mV
Vi(p-p)
peak-to-peak input
voltage
[3] 1.66
1.83
2.35
V
Digital outputs D9 to D0 and IR (Referenced to VSSD)
VOL
LOW-level output
IO = 1 mA
voltage
0
-
0.5
V
VOH
HIGH-level output
IO = 1 mA
voltage
VDDO 0.5 -
VCCO
V
IOZ
OFF-state output current 0.5 V < VO < VDDO
20
-
Switching characteristics; Clock input CLK; see Figure 4[1]
+20
A
fclk(max)
maximum clock
frequency
20
-
-
MHz
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Analog signal processing (fclk = 20 MHz)
Linearity
15
-
-
ns
15
-
-
ns
INL
integral non-linearity
ramp input; see Figure 6
-
1
2
LSB
DNL
differential non-linearity ramp input; see Figure 7
-
0.25
0.7
LSB
Input set response; see Figure 8[4]
ts(LH)
LOW to HIGH settling full-scale square wave
-
time
4
6
ns
ts(HL)
HIGH to LOW settling full-scale square wave
-
time
4
6
ns
Harmonics; see Figure 9[5]
THD
total harmonic distortion fi = 1 MHz
Signal-to-Noise ratio; see Figure 9[5]
-
63
-
dB
S/N
signal-to-noise ratio
Effective bits; see Figure 9[5]
without harmonics;
fi = 1 MHz
-
60
-
dB
ENOB
effective number of bits
fi = 300 KHz
fi = 1 MHz
fi = 3.58 MHz
-
9.5
-
bits
-
9.3
bits
-
8.0
bits
ADC1002S020_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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