ATC18RHA(2005) 데이터 시트보기 (PDF) - Atmel Corporation

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ATC18RHA
(Rev.:2005)

Rad. Hard 0.18 µm CMOS Cell-based ASIC for Space Use

Atmel Corporation 

Advanced

Packaging

ATC18RHA

In a similar vein, access to microcontroller, DSP, and SRAM blocks must be provided so that

controllability and observability of the inputs and outputs to the blocks are achieved with the min-

imum amount of preconditioning. SRAM blocks need to provide access to both address and data

ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a

method for providing this accessibility.

The glue logic can be designed using full SCAN techniques to enhance its testability.

It should be noted that, in almost all of these cases, the purpose of the testability technique is to

provide Atmel a means to assess the structural integrity of the chip, i.e., sort devices with manu-

facturing-induced defects. All of the techniques described above should be considered

supplemental to a set of patterns which exercise the functionality of the design in its anticipated

operating modes.

The ATC18RHA Series are offered in ceramic packages: multi layers quad flat packs (MQFP)

with up to 352 pins and a BGA based on ceramic land grid arrays, so called multi layer column

grid array (MCGA) with up to 625 pins.

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4261B–AERO–06/05

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