CY2291 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY2291 Datasheet PDF : 14 Pages
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CY2291
Switching Characteristics, Commercial 3.3V
Parameter
t1
t3
t4
t5
t6
t7
t8
t9A
t9B
t9C
t9D
t10A
t10B
Name
Output Period
Output Duty
Cycle[11]
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter[14]
Clock Jitter[14]
Clock Jitter[14]
Clock Jitter[14]
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
Description
Clock output range, 3.3V CY2291
operation
CY2291F
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHZ
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHZ
Output clock rise time[13]
Output clock fall time[13]
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related
outputs[3, 12, 15]
Frequency transition rate
Peak-to-peak period jitter (t9A Max. – t9A
min.),% of clock period (fOUT < 4 MHz)
Peak-to-peak period jitter (t9B Max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
Peak-to-peak period jitter
(fOUT > 50 MHz)
Lock Time from Power-Up
Lock Time from Power-Up
CPU PLL Slew Limits
CY2291
CY2291F
Min.
12.5
(80 MHz)
15
(66.6 MHz)
40%
Typ.
50%
Max.
13000
(76.923 kHz)
13000
(76.923 kHz)
60%
45%
50%
55%
3
5
2.5
4
10
15
10
15
< 0.25
0.5
1.0
20.0
<0.5
1
<0.7
1
<400
500
<250
350
<25
50
<0.25
1
8
80
8
66.6
Unit
ns
ns
ns
ns
ns
ns
ns
MHz/
ms
%
ns
ps
ps
ms
ms
MHz
MHz
Document #: 38-07189 Rev. *A
Page 8 of 14
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