CY7C1061AV33-8ZI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1061AV33-8ZI

1M x 16 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS

tRC

CE1

CE2

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

Write Cycle No. 1 (CE Controlled)[13, 14, 15]

CY7C1061AV33

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

ISB

tWC

ADDRESS

CE

tSA

tSCE

WE

BHE, BLE

DATAI/O

tAW

tPWE

tBW

tSD

Notes:

12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.

14. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.

tHA

tHD

Document #: 38-05256 Rev. *D

Page 6 of 11

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