CY7C1320BV18-200BZC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1320BV18-200BZC

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

Logic Block Diagram (CY7C1318BV18)

Burst

A0

Logic

20 19

A(19:0)

A(19:1)

LD

Address

Register

K

K

DOFF

CLK

Gen.

VREF

R/W

BWS[1:0]

Control

Logic

Write

Reg

Write

Reg

1M x 18 Array

Read Data Reg.

36 18

18

Output

R/W

Logic

Control

C

C

Reg.

Reg.

Reg.

18

18

18

CQ

CQ

DQ[17:0]

Logic Block Diagram (CY7C1320BV18)

Burst

A0

Logic

19 18

A(18:0)

A(18:1)

LD

Address

Register

K

K

DOFF

CLK

Gen.

Write

Reg

Write

Reg

512K x 36 Array

Read Data Reg.

VREF

R/W

BWS[3:0]

Control

Logic

72 36

36

36

Output

R/W

Logic

Control

C

C

Reg.

Reg. 36

Reg.

36

36

CQ

CQ

DQ[35:0]

Document Number: 38-05621 Rev. *C

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