Fig. 1: Maximum RMS power dissipation
versus RMS on-state current.
P (W)
7
180 º
α
6α
α = 180 º
5
α = 120 º
4
α = 90 º
3
α = 60 º
2
α = 30 º
1
0
0
1
IT(RMS)(A)
2
3
4
Fig. 3: RMS on-state current versus case
temperature.
I T(RMS) (A)
1
0.8
α = 180 º
0.6
0.4
0.2
0
Tamb (ºC)
0 10 20 30 40 50 60 70 80 90 100 110 120 130
Fig. 5: Relative variation of gate trigger current
and holding current versus junction temperature.
Igt (Tj)
Igt (Tj = 25 ºC)
2.6
Ih (Tj)
Ih (Tj = 25 ºC)
2.4
2.2
2.0
Igt
1.8
1.6
1.4
1.2 Ih
1.0
0.8
0.6
0.4
Tj (ºC)
-40 -20 0 20 40 60 80 100 120 140
FT04...I
LOGIC LEVEL TRIAC
Fig. 2: Correlation between maximum
RMS power dissipation and maximum
allowable temperature (Tamb and T case).
P (W)
7
T case (ºC)
6
-75
Rth (j-c)
5
-85
4
3
2
Rth (j-a)
1
-95
-105
-115
0
-125 Tamb (ºC)
0 20 40 60 80 100 120 140
Fig. 4: Relative variation of thermal impedance
junction to ambient versus pulse duration.
Zth(j-a) / Rth(j-a)
1.00
0.10
0.01
tp (s)
1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2
Fig. 6: Non repetitive surge peak on-state
current versus number of cycles.
I TSM (A)
20
Tj initial = 25 ºC
15
10
5
0
Number of cycles
1
10
100
1000
Jul - 02