83940AY-02LFT 데이터 시트보기 (PDF) - Integrated Device Technology

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83940AY-02LFT

LOW SKEW, 1-TO-18 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Device Technology 

ICS83940-02

LOW SKEW, 1-TO-18

DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 2, 12, 17, 25

GND

Power

Output supply ground.

3

LVCMOS_CLK

Input Pulldown Clock input. LVCMOS/LVTTL interface levels.

Clock select input. Selects LVCMOS clock input

4

CLK_SEL

Input Pulldown when HIGH. Selects CLK0, nCLK0 inputs when

LOW. LVCMOS/LVTTL itnerface levels.

5

CLK0

Input Pulldown Non-inverting differential clock input.

6

nCLK0

Input Pullup Inverting differential clock input

7

8, 16, 21, 29

9, 10, 11, 13, 14,

15, 18, 19, 20, 22,

23, 24, 26, 27, 28,

30, 31, 32

VDD

VDDO

Q17, Q16, Q15, Q14, Q13,

Q12, Q11, Q10, Q9, Q8,

Q7, Q6, Q5, Q4, Q3,

Q2, Q1, Q0

Power

Power

Output

Core supply pin.

Output supply pins.

Clock outputs. 7Ω typical output impedance.

LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

Parameter

Input Capacitance

CPD

Power Dissipation Capacitance

(per output)

RPULLUP

RPULLDOWN

ROUT

Input Pullup Resistor

Input Pulldown Resistor

Output Impedance

Test Conditions

VDD, VDDO = 3.465V

VDD = 3.465V, VDDO = 2.625V

VDD, VDDO = 2.625V

Minimum Typical Maximum Units

4

pF

12

pF

18

pF

18

pF

51

KΩ

51

KΩ

5

7

12

Ω

TABLE 3A. CLOCK SELECT FUNCTION TABLE

Control Input

CLK_SEL

0

1

CLK0, nCLK0

Selected

De-selected

Clock

LVCMOS_CLK

De-selected

Selected

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

CLK_SEL LVCMOS_CLK

CLK0

nCLK0

Outputs

Q0:Q17

Input to Output Mode

Polarity

0

—

0

1

LOW Differential to Single Ended Non Inverting

0

—

1

0

HIGH Differential to Single Ended Non Inverting

0

—

0

Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting

0

—

1

Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting

0

—

Biased; NOTE 1

0

HIGH Single Ended to Single Ended Inverting

0

—

Biased; NOTE 1

1

LOW Single Ended to Single Ended Inverting

1

0

—

—

LOW Single Ended to Single Ended Non Inverting

1

1

—

—

HIGH Single Ended to Single Ended Non Inverting

NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".

83940AY-02

www.idt.com

REV. A AUGUST 4, 2010

2

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