ICS8344AYI-01LFT 데이터 시트보기 (PDF) - Integrated Device Technology
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ICS8344AYI-01LFT
Integrated Device Technology
ICS8344AYI-01LFT Datasheet PDF : 13 Pages
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ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q16 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
13
15, 19
16
VDDO
GND
CLK_SEL
VDD
nCLK1
Power
Output supply pins.
Power
Input
Power
Input
Power supply ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
Core supply pins.
Pullup Inverting differential LVPECL clock input.
17
CLK1
Input Pulldown Non-inverting differential LVPECL clock input.
20
nCLK0
Input Pullup Inverting differential LVPECL clock input.
21
CLK0
Input Pulldown Non-inverting differential LVPECL clock input.
22
CLK_EN
Input
Pullup
Synchronizing control for enabling and disabling clock
outputs. LVCMOS interface levels.
23
OE
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q23. LVCMOS / LVTTL interface levels.
24
nc
Unused
No connect.
25, 26, 29, 30
31, 32, 35, 36
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Output
Q0 thru Q7 outputs. 7Ω typical output impedance.
37, 38, 41, 42
43, 44, 47, 48
Q8, Q9, Q10, Q11
Q12, Q13, Q14, Q15
Output
Q8 thru Q15 outputs. 7Ω typical output impedance.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
CPD
RPULLUP
RPULLDOWN
ROUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum Typical Maximum Units
4
pF
pF
51
KW
51
KΩ
5
7
12
Ω
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
2
ICS8344AYI-01 REV. B MAY 10, 2007
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