LH543601 데이터 시트보기 (PDF) - Sharp Electronics

부품명

상세내역

제조사

LH543601

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

256 × 36 × 2 Bidirectional FIFO

PORT B WORD-WIDTH SELECTION

LH543601

PORT

A

36-Bit Data Stream

18-Bit Data Streams

D35A

Bits 18-35

(2nd Halfword)

D35B

18

D18A

(2Bnitds H18a-lf3w5ord)

18

B(i1tsst0H-1a7lfword)

D18B

D17A

D17B

18

18

D0A

Bits 0-17

(1st Halfword)

D0B

2nd Halfword, then 1st Halfword

PORT

B

1st Halfword, then 2nd Halfword

543601-32

Figure 6a. 36-to-18 Funneling Through FIFO #1

36-Bit Data Stream

D35A

9

D27A

Bits 27-35

(4th Byte)

9-Bit Data Streams

D35B

9

D27B

4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte

PORT

A

D26A

9

D18A

D17A

9

D9A

Bits 18-26

(3rd Byte)

Bits 9-17

(2nd Byte)

D26B

9

D18B

D17B

9

D9B

3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte

PORT

B

2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte

D8A

9

D0A

Bits 0-8

(1st Byte)

D8B

9

D0B

1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte

543601-34

Figure 6b. 36-to-9 Funneling Through FIFO #1

NOTES:

1. The heavy black borders on register segments indicate the main

data path, suitable for most applications. Alternate paths feature

a different ordering of bytes within a word, at Port B.

2. The funneling process does not change the ordering of bits within

a byte. Halfwords (Figure 6a) or bytes (Figure 6b) are trans-

ferred in parallel form from Port A to Port B.

3. The word-width setting may be changed during system operation;

however, two clock intervals should be allowed for these signals

to settle, before again attempting to read D0B – D35B, and three

dummy words should be passed through initially. Also, incom-

plete data words may occur, when the word width is changed

from shorter to longer at an inappropriate point in the data block

passing through the FIFO.

15

Share Link: