LH543601 데이터 시트보기 (PDF) - Sharp Electronics
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LH543601 Datasheet PDF : 43 Pages
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256 × 36 × 2 Bidirectional FIFO
TIMING DIAGRAMS (cont’d)
CKA
R/WA
ENA
REQA
A2A
A1A
A0A
READ FROM
FIFO #2
t CC
WRITE TO
FIFO #1
t CH
t CL
tRWS
t RWH
tRWS tRWH
tES
tEH
t ES
t EH
tRQS
tRQH
tRQS
tRQH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
OEA
tA
tZX
tA
t OH
t XZ
t DS
t DH
D0A - D35A
PREVIOUS
DATA
tPF
DATA OUT
tPF
DATA IN
tPF
PFA
VALID PF
VALID PF
VALID PF
NOTES:
1. The Port A Parity Error Flag (PFA) reflects the parity status of data present on the data bus.
2. The status of OEA does not gate read or write operations.
3. If OEA is left LOW during a write operation, then the previous data held in the output latch is
written back into FIFO #1.
Figure 10. Port A FIFO Read/Write
LH543601
543601-24
19
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